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1 of 31 april 11, 2007 ? 2007 integrated device technology, inc. *notice: the information in this document is subject to change without notice dsc 6925 idt and the idt logo are registered trademarks of integrated device technology, inc. ? device overview the 89hpes24nt3 is a member of the idt precise? family of pci express? switching solutions offering the next-generation i/o inter- connect standard. the pes24nt3 is a 24-lane, 3-port peripheral chip that performs pci express base switching with a feature set optimized for high performance applications such as servers, storage, and commu- nications/networking. it provides high-performance switching functions between a pcie? upstream port, a transparent downstream port, and a non-transparent downstream port. with non-transparent bridging (ntb) functionality, the pes24nt3 can be used standalone or as a chipset with idt pcie system intercon- nect switches in multi-host and intelligent i/o applications such as communications, storage, and blade servers where inter-domain communication is required. features high performance pci express switch ? twenty-four pci express lanes (2.5gbps), three switch ports ? delivers 96 gbps (12 gbps) of aggregate switching capacity ? low latency cut-through switch architecture ? support for max payload size up to 2048 bytes ? supports one virtual channel and eight traffic classes ? pci express base specification revision 1.0a compliant flexible architecture with numerous configuration options ? port arbitration schemes utilizing round robin ? supports automatic per port link width negotiation (x8, x4, x2, or x1) ? static lane reversal on all ports ? automatic polarity inversion on all lanes ? supports locked transactions, allowing use with legacy soft- ware ? ability to load device configuration from serial eeprom ? ability to control device via smbus non-transparent port ? crosslink support on ntb port ? four mapping windows supported ? each may be configured as a 32-bit memory or i/o window ? may be paired to form a 64-bit memory window ? interprocessor communication ? thirty-two inbound and outbound doorbells ? four inbound and outbound message registers ? two shared scratchpad registers ? allows up to sixteen masters to communicate through the non- transparent port ? no limit on the number of supported outstanding transactions through the non-transparent bridge ? completely symmetric non-transparent bridge operation allows similar/same configuration software to be run ? supports direct connection to a transparent or non-transparent port of another switch block diagram figure 1 internal block diagram 24 pci express lanes x8 upstream port and two x8 downstream ports serdes phy logical layer serdes phy logical layer serdes phy logical layer ... multiplexer / demultiplexer 3-port switch core frame buffer route table port arbitration scheduler transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer ... multiplexer / demultiplexer transaction layer data link layer serdes phy logical layer serdes phy logical layer serdes phy logical layer ... multiplexer / demultiplexer transaction layer data link layer non- transparent bridge 89hpes24nt3 data sheet preliminary information* 24-lane 3-port non-transparent pci express? switch
2 of 31 april 11, 2007 idt 89hpes24nt3 data sheet *notice: the information in this document is subject to change without notice highly integrated solution ? requires no external components ? incorporates on-chip internal memory for packet buffering and queueing ? integrates twenty-four 2.5 gbps embedded full duplex serdes, 8b/10b encoder/decoder (no separate transceivers needed) reliability, availability, and serviceability (ras) features ? upstream port can be dynamically swapped with non-trans- parent downstream port to support failover applications ? internal end-to-end parity protection on all tlps ensures data integrity even in systems that do not implement end-to-end crc (ecrc) ? supports ecrc pass-through in transparent and non-trans- parent ports ? supports hot-swap power management ? supports pci power management interface specification, revision 1.1 (pci-pm) ? unused serdes are disabled testability and debug features ? built in serdes pseudo-random bit stream (prbs) generator ? ability to read and write any internal register via the smbus ? ability to bypass link training and force any link into any mode ? provides statistics and performance counters two smbus interfaces ? slave interface provides full access to all software-visible registers by an external smbus master ? master interface provides connection for an optional serial eeprom used for initialization ? master interface is also used by an external hot-plug i/o expander ? master and slave interfaces may be tied together so the switch can act as both master and slave eight general purpose input/output pins packaged in 27x27mm 420-ball bga with 1mm ball spacing product description utilizing standard pci express interconnect, the pes24nt3 provides the most efficient high-performance i/o connectivity solution for applica- tions requiring high throughput, low latency, and simple board layout with a minimum number of board layers. with support for non-trans- parent bridging, the pes24nt3, as a standalone switch or as a chipset with idt pcie system interconnect switches, enables multi-host and intelligent i/o applications requiri ng inter-domain communication. the pes24nt3 provides 96 gbps (12 gbps) of aggregated, full-duplex switching capacity through 24 integrated serial lanes, using proven and robust idt technology. each lane provides 2.5 gbps of bandwidth in both directions and is fully compliant with pci express base specifica- tion 1.0a. the pes24nt3 is based on a flexible and efficient layered architec- ture. the pci express layer consists of serdes, physical, data link and transaction layers in compliance with pci express base specification revision 1.0a. the pes24nt3 can operate either as a store and forward or cut-through switch depending on the packet size and is designed to switch memory and i/o transactions. it supports eight traffic classes (tcs) and one virtual channel (vc) with sophisticated resource management. this includes round robin port arbitration, guar- anteeing bandwidth allocation and/or latency for critical traffic classes in applications such as high throughput 10 gbe i/os, sata controllers, and fibre channel hbas. switch configuration the pes24nt3 is a three port switch that contains 24 pci express lanes. each of the three ports is statically allocated 8 lanes with ports labeled as a, b and c. port a is the upstream port, port b is the trans- parent downstream port, and port c is the non-transparent downstream port. during link training, link width is automatically negotiated. each pes24nt3 port is capable of independently negotiating to a x8, x4, x2 or x1 width. thus, the pes24nt3 may be used in virtually any three port switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.). the pes24nt3 supports static l ane reversal. for example, lane reversal for upstream port a may be configured by asserting the pci express port a lane reverse (pealrev) input signal or through serial eeprom or smbus initialization. lane reversal for ports b and c may be enabled via a configuration space r egister, serial eeprom, or the smbus.
3 of 31 april 11, 2007 idt 89hpes24nt3 data sheet figure 2 pcie system interco nnect architecture block diagram figure 3 dual host storage system pes24nt3 cpu pcie system interconnect switch pes24nt3 cpu pes24nt3 cpu embedded fc cpu embedded sata / sas cpu embedded gbe / 10gige cpu pcie system interconnect switch cpu pes24n3 fc controller x8 pcie cpu pes24n3 fc controller storage to server to se r ve r cache maint. & possible data flow x8 pcie controller 1 controller 2 x8 pcie fc 2gb/s and 4gb/s fc 2gb/s and 4gb/s
4 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pin description the following tables list the functions of the pins provided on the pes24nt3. some of the functions listed may be multiplexed o nto the same pin. the active polarity of a signal is defined using a suffix. signals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses, and select li nes) will be interpreted as being active, or asserted, when at a logic one (high) level. signal type name/description pealrev i pci express port a lane reverse. when this bit is asserted, the lanes of pci express port a are reversed. this value may be overridden by modify- ing the value of the palrev bit in the pa_swctl register. pearp[7:0] pearn[7:0] i pci express port a serial data receive. differential pci express receive pairs for port a. peatp[7:0] peatn[7:0 o pci express port a serial data transmit. differential pci express trans- mit pairs for port a peblrev i pci express port b lane reverse. when this bit is asserted, the lanes of pci express port b are reversed. this value may be overridden by modify- ing the value of the pblrev bit in the pa_swctl register. pebrp[7:0] pebrn[7:0] i pci express port b serial data receive. differential pci express receive pairs for port b. pebtp[7:0] pebtn[7:0] o pci express port b serial data transmit. differential pci express trans- mit pairs for port b peclrev i pci express port c lane reverse. when this bit is asserted, the lanes of pci express port c are reversed. this value may be overridden by modify- ing the value of the pclrev bit in the pa_swctl register. pecrp[7:0] pecrn[7:0] i pci express port c serial data receive. differential pci express receive pairs for port c. pectp[7:0] pectn[7:0] o pci express port c serial data transmit. differential pci express trans- mit pairs for port c perefclkp[1:0] perefclkn[1:0] i pci express reference clock. differential reference clock pair input. this clock is used as the reference clock by on-chip plls to generate the clocks required for the system logic and on-chip serdes. the frequency of the dif- ferential reference clock is determined by the refclkm signal. refclkm i pci express reference clock mode select. these signals select the fre- quency of the reference clock input. 0x0 - 100 mhz 0x1 - 125 mhz table 1 pci express interface pins signal type name/description msmbaddr[4:1] i master smbus address. these pins determine the smbus address of the serial eeprom from which configuration information is loaded. msmbclk i/o master smbus clock. this bidirectional signal is used to synchronize transfers on the master smbus. it is active and generating the clock only when the eeprom or i/o expanders are being accessed. msmbdat i/o master smbus data. this bidirectional signal is used for data on the mas- ter smbus. table 2 smbus interface pins (part 1 of 2)
5 of 31 april 11, 2007 idt 89hpes24nt3 data sheet ssmbaddr[5,3:1] i slave smbus address. these pins determine the smbus address to which the slave smbus interface responds. ssmbclk i/o slave smbus clock. this bidirectional signal is used to synchronize trans- fers on the slave smbus. ssmbdat i/o slave smbus data. this bidirectional signal is used for data on the slave smbus. signal type name/description gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pebrstn alternate function pin type: output alternate function: reset output for downstream port b gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pecrstn alternate function pin type: output alternate function: reset output for downstream port c gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: palinkupn alternate function pin type: output alternate function: port a link up status output gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pblinkupn alternate function pin type: output alternate function: port b link up status output gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pclinkupn alternate function pin type: output alternate function: port c link up status output gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: failoverp alternate function pin type: input alternate function: ntb upstream port failover gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. table 3 general purpose i/o pins signal type name/description table 2 smbus interface pins (part 2 of 2)
6 of 31 april 11, 2007 idt 89hpes24nt3 data sheet signal type name/description cclkds i common clock downstream. when the cclkds pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. cclkus i common clock upstream. when the cclkus pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. msmbsmode i master smbus slow mode. the assertion of this pin indicates that the master smbus should operate at 100 khz instead of 400 khz. this value may not be overridden. pentbrstn i non-transparent bridge reset. assertion of this signal indicates a reset on the external side of the non-transparent bridge. this signal is only used when the switch mode selects a non-transparent mode and has no effect otherwise. perstn i fundamental reset. assertion of this signal resets all logic inside the pes24nt3 and initiates a pci express fundamental reset. rsthalt i reset halt. when this signal is asserted during a pci express fundamental reset, the pes24nt3 executes the reset procedure and remains in a reset state with the master and slave smbuses active. this allows software to read and write registers internal to the device before normal device opera- tion begins. the device exits the reset state when the rsthalt bit is cleared in the pa_swctl register by an smbus master. swmode[3:0] i switch mode. these configuration pins determine the pes24nt3 switch operating mode. 0x0 - reserved 0x1 - reserved 0x2 - non-transparent mode 0x3 - non-transparent mode with serial eeprom initialization 0x4 - non-transparent failover mode 0x5 - non-transparent failover mode with serial eeprom initialization 0x6 through 0xf - reserved table 4 system pins signal type name/description jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic or jtag controller. jtag_tck is independent of the system clock with a nominal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic or jtag controller. table 5 test pins (part 1 of 2)
7 of 31 april 11, 2007 idt 89hpes24nt3 data sheet jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic or jtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic and jtag tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board signal type name/description v dd core i core v dd . power supply for core logic. v dd io i i/o v dd . lvttl i/o buffer power supply. v dd pe i pci express digital power. pci express digital power used by the digital power of the serdes. v dd ape i pci express analog power. pci express analog power used by the pll and bias generator. v tt pe i pci express termination power. v ss i ground. table 6 power and ground pins signal type name/description table 5 test pins (part 2 of 2)
8 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pin characteristics note: some input pads of the pes24nt3 do not contain internal pu ll-ups or pull-downs. unused inputs should be tied off to appropriate levels. this is especially critical for unused control signal i nputs which, if left floating, could adversely affect operation. also, any input pin left floating can cause a slight in crease in power consumption. function pin name type buffer i/o type internal resistor notes pci express inter- face pealrev i lvttl input pull-down pearn[7:0] i cml serial link pearp[7:0] i peatn[7:0] o peatp[7:0] o peblrev i lvttl input pull-down pebrn[7:0] i cml serial link pebrp[7:0] i pebtn[7:0] o pebtp[7:0] o peclrev i lvttl input pull-down pecrn[7:0] i cml serial link pecrp[7:0] i pectn[7:0] o pectp[7:0] o perefclkn[1:0] i lvpecl/ cml diff. clock input refer to table 8 perefclkp[1:0] i refclkm i lvttl input pull-down smbus msmbaddr[4:1] i lvttl input pull-up msmbclk i/o sti msmbdat i/o ssmbaddr[5,3:1] i input pull-up ssmbclk i/o sti ssmbdat i/o general purpose i/o gpio[7:0] i/o lvttl input, high drive pull-up system pins cclkds i lvttl input pull-up cclkus i pull-up msmbsmode i pull-down pentbrstn i perstn i rsthalt i pull-down swmode[3:0] i pull-up table 7 pin characteristics (part 1 of 2)
9 of 31 april 11, 2007 idt 89hpes24nt3 data sheet jtag jtag_tck i lvttl sti pull-up jtag_tdi i pull-up jtag_tdo o low drive jtag_tms i sti pull-up jtag_trst_n i pull-up external pull-down function pin name type buffer i/o type internal resistor notes table 7 pin characteristics (part 2 of 2)
10 of 31 april 11, 2007 idt 89hpes24nt3 data sheet logic diagram ? pes24nt3 figure 4 pes24nt3 logic diagram reference clocks perefclkp perefclkn peatp[0] peatn[0] jtag_tck gpio[7:0] 8 general purpose i/o v dd core v dd io v dd pe v dd ape power/ground pearp[0] pearn[0] pearp[1] pearn[1] pearp[7] pearn[7] pci express switch serdes input peatp[1] peatn[1] peatp[7] peatn[7] pci express switch serdes output ... msmbaddr[4:1] msmbclk msmbdat 4 ssmbaddr[5,3:1] ssmbclk ssmbdat 4 master smbus interface slave smbus interface cclkus rsthalt system functions jtag_tdi jtag_tdo jtag_tms jtag_trst_n jtag v ss swmode[3:0] 4 2 2 port a port a pebtp[0] pebtn[0] pebrp[0] pebrn[0] pebrp[1] pebrn[1] pebrp[7] pebrn[7] pci express switch serdes input pebtp[1] pebtn[1] pebtp[7] pebtn[7] pci express switch serdes output ... ... port b port b pectp[0] pectn[0] pecrp[0] pecrn[0] pecrp[1] pecrn[1] pecrp[7] pecrn[7] pci express switch serdes input pectp[1] pectn[1] pectp[7] pectn[7] pci express switch serdes output ... port c port c pes24nt3 pealrev cclkds peblrev peclrev perstn refclkm msmbsmode ... ... v tt pe pentbrstn pentbrstn
11 of 31 april 11, 2007 idt 89hpes24nt3 data sheet system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 12 and 13. ac timing characteristics parameter description min typical max unit refclk freq input reference clock frequency range 100 125 1 1. the input clock frequency will be either 100 or 125 mhz depending on signal refclkm. mhz refclk dc 2 2. clkin must be ac coupled. use 0.01 ? 0.1 f ceramic capacitors. duty cycle of input clock 40 50 60 % t r , t f rise/fall time of input clocks 0.2*rcui rcui 3 3. rcui (reference clock unit interval) refers to the reference clock period. v sw differential input voltage swing 4 4. ac coupling required. 0.6 1.6 v t jitter input clock jitter (cycle-to-cycle) 125 ps table 8 input clock requirements parameter description min 1 1. minimum, typical, and maximum values meet the requirements under pci specification 1.1 typical 1 max 1 units pcie transmit ui unit interval 399.88 400 400.12 ps t tx-eye minimum tx eye width 0.7 .9 ui t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui t tx-rise , t tx-fall d+ / d- tx output rise/fall time 50 90 ps t tx- idle-min minimum time in idle 50 ui t tx-idle-set-to- idle maximum time to transition to a valid idle after sending an idle ordered set 20 ui t tx-idle-to-diff- data maximum time to transition from valid idle to diff data 20 ui t tx-skew transmitter data skew between any 2 lanes 500 1300 ps pcie receive ui unit interval 399.88 400 400.12 ps t rx-eye (with jitter) minimum receiver eye width (jitter tolerance) 0.4 ui t rx-eye-medium to max jitter max time between jitter median & max deviation 0.3 ui t rx-idle-det-diff- enter time unexpected idle enter detect threshold integration time 10 ms t rx-skew lane to lane input skew 20 ns table 9 pcie ac timing characteristics
12 of 31 april 11, 2007 idt 89hpes24nt3 data sheet signal symbol reference edge min max unit timing diagram reference gpio gpio[7:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 50 ? ns table 10 gpio ac timing characteristics signal symbol reference edge min max unit timing diagram reference jtag jtag_tck tper_16a none 50.0 ? ns see figure 5. thigh_16a, tlow_16a 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149.1, recommends that jtag_tms should be held at 1 while the signal applied at jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going from low to high) on a rising edge of jtag _tck when jtag_tms is low, because the tap controller might go to either the run-test/idle state or stay in the test-logic-reset sta te. tsu_16b jtag_tck rising 2.4 ? ns thld_16b 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 20 ns tdz_16c 2 2. the values for this symbol were determined by calculation, not by testing. ?20ns jtag_trst_n tpw_16d 2 none 25.0 ? ns table 11 jtag ac timing characteristics
13 of 31 april 11, 2007 idt 89hpes24nt3 data sheet figure 5 jtag ac timing waveform recommended operating supply voltages power-up sequence this section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper func tionality. for the pes24nt3, the power-up sequence must be as follows: 1. v dd i/o ? 3.3v 2. v dd core, v dd pe, v dd ape ? 1.0v 3. v tt pe ? 1.5v when powering up, each voltage level must ramp and stabilize prio r to applying the next voltage in the sequence to ensure inter nal latch-up issues are avoided. there are no maximum time limitations in ramping to valid power levels. the power-down sequence must be in the rev erse order of the power-up sequence. symbol parameter minimum typical maximum unit v dd core internal logic supply 0.9 1.0 1.1 v v dd i/o i/o supply except for serdes lvpecl/cml 3.0 3.3 3.6 v v dd pe pci express digital power 0.9 1.0 1.1 v v dd ape pci express analog power 0.9 1.0 1.1 v v tt pe pci express serial data transmit termina- tion voltage 1.425 1.5 1.575 v v ss common ground 0 0 0 v table 12 pes24nt3 operating voltages tpw_16d tdz_16c tdo_16c thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms jtag_tdo jtag_trst_n
14 of 31 april 11, 2007 idt 89hpes24nt3 data sheet recommended operating temperature power consumption typical power is measured under the following conditions: 25c ambient, 35% total link usage on all ports, typical voltages def ined in table 14. maximum power is measured under the following conditions: 70c ambient, 85% total link usage on all ports, maximum voltages def ined in table 14. all power measurements assume that the part is mount ed on a 10 layer printed circuit board with 0 lfm airflow. grade temperature commercial 0 c to +70 c ambient table 13 pes24nt3 operating temperatures number of connected lanes: port-a/port-b/port-c core (watts) (1.0v supply) pcie digital (watts) (1.0v supply) pcie analog (watts) (1.0v supply) pcie termin- ation (watts) (1.5v supply) i/o (watts) (3.3v supply) total (watts) typ max typ max typ max typ max typ max typ max 8/4/4 0.59 0.84 0.75 1.08 0.33 0.42 0.62 0.78 0.002 0.01 2.3 3.12 8/8/8 0.68 0.95 0.98 1.43 0.38 0.48 0.88 1.01 0.002 0.01 2.92 3.88 table 14 pes24nt3 power consumption
15 of 31 april 11, 2007 idt 89hpes24nt3 data sheet dc electrical characteristics values based on systems running at recommended supply voltages, as shown in table 12. note: see table 7, pin characteristics, for a complete i/o listing. i/o type parameter description min 1 typ 1 max 1 unit conditions serial link pcie transmit v tx-diffp-p differential peak-to-peak output voltage 800 1200 mv v tx-de-ratio de-emphasized differential output voltage -3 -4 db v tx-dc-cm dc common mode voltage -0.1 1 3.7 v v tx-cm-acp rms ac peak common mode output volt- age 20 mv v tx-cm-dc- active-idle-delta abs delta of dc common mode voltage between l0 and idle 100 mv v tx-cm-dc-line- delta abs delta of dc common mode voltage between d+ and d- 25 mv v tx-idle-diffp electrical idle diff peak output 20 mv serial link (cont.) v tx-rcv-detect voltage change during receiver detection 600 mv rl tx-diff transmitter differential return loss 12 db rl tx-cm transmitter common mode return loss 6 db z tx-deff-dc dc differential tx impedance 80 100 120 z ose single ended tx impedance 40 50 60 transmitter eye diagram tx eye height (de-emphasized bits) 505 650 mv transmitter eye diagram tx eye height (transition bits) 800 950 mv pcie receive v rx-diffp-p differential input voltage (peak-to-peak) 175 1200 mv v rx-cm-ac receiver common-mode voltage for ac coupling 150 mv rl rx-diff receiver differential return loss 15 db rl rx-cm receiver common mode return loss 6 db z rx-diff-dc differential input impedance (dc) 80 100 120 z rx-comm-dc single-ended input impedance 40 50 60 z rx-comm-high- z-dc powered down input common mode impedance (dc) 200k 350k v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv pcie refclk c in input capacitance 1.5 ? pf table 15 dc electrical characteristics (part 1 of 2)
16 of 31 april 11, 2007 idt 89hpes24nt3 data sheet other i/os low drive output i ol ?2.5?ma v ol = 0.4v i oh ?-5.5?ma v oh = 1.5v high drive output i ol ? 12.0 ? ma v ol = 0.4v i oh ?-20.0?ma v oh = 1.5v schmitt trig- ger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? input v il -0.3 ? 0.8 v ? v ih 2.0 ? v dd io + 0.5 v? capacitance c in ??8.5pf ? leakage inputs ? ? + 10 av dd i/o (max) i/o leak w / o pull-ups/downs ??+ 10 av dd i/o (max) i/o leak with pull-ups/downs ??+ 80 av dd i/o (max) 1. minimum, typical, and maximum values meet the requirements under pci specification 1.0a. i/o type parameter description min 1 typ 1 max 1 unit conditions table 15 dc electrical characteristics (part 2 of 2)
17 of 31 april 11, 2007 idt 89hpes24nt3 data sheet package pinout ? 420-bga signal pinout for pes24nt3 the following table lists the pin numbers and signal names for the pes24nt3 device. pin function alt pin function alt pin function alt pin function alt a1 v ss b9 msmbdat c17 v dd io d25 v ss a2 v ss b10 ssmbaddr_2 c18 v ss d26 perefclkn2 a3 v ss b11 ssmbaddr_5 c19 v dd io e1 v ss a4 jtag_tdi b12 ssmbdat c20 v ss e2 v ss a5 jtag_tms b13 pealrev c21 v dd io e3 v ss a6 msmbaddr_1 b14 swmode_0 c22 v ss e4 v ss a7 msmbaddr_3 b15 swmode_2 c23 v dd io e5 v ss a8 msmbclk b16 peclrev c24 v ss e6 v dd core a9 ssmbaddr_1 b17 pentbrstn c25 v ss e7 v dd core a10 ssmbaddr_3 b18 gpio_00 1 c26 perefclkp2 e8 v ss a11 ssmbclk b19 gpio_02 1 d1 perefclkp1 e9 v dd core a12 cclkus b20 gpio_04 1 d2 v ss e10 v ss a13 cclkds b21 gpio_06 d3 v ss e11 v dd core a14 peblrev b22 msmbsmode d4 v ss e12 v ss a15 swmode_1 b23 refclkm d5 v dd core e13 v dd core a16 swmode_3 b24 v dd io d6 v dd core e14 v ss a17 perstn b25 v ss d7 v ss e15 v dd core a18 rsthalt b26 v ss d8 v dd core e16 v ss a19 gpio_01 1 c1 perefclkn1 d9 v ss e17 v dd core a20 gpio_03 1 c2 v ss d10 v dd core e18 v ss a21 gpio_05 1 c3 v ss d11 v ss e19 v dd core a22 gpio_07 c4 v dd core d12 v dd core e20 v dd core a23 v ss c5 v dd io d13 v dd core e21 v dd core a24 v ss c6 v ss d14 v ss e22 v ss a25 v ss c7 v dd io d15 v dd core e23 v ss a26 v ss c8 v ss d16 v ss e24 v ss b1 v ss c9 v dd io d17 v dd core e25 v ss b2 v ss c10 v ss d18 v dd core e26 v ss b3 v dd io c11 v dd io d19 v dd core f1 v dd core b4 jtag_tck c12 v ss d20 v ss f2 v dd core b5 jtag-tdo c13 v dd io d21 v dd core f3 v dd ape b6 jtag-trst_n c14 v dd core d22 v dd core f4 v ss b7 msmbaddr_2 c15 v dd io d23 v ss f5 v ss b8 msmbaddr_4 c16 v dd core d24 v ss f22 v ss table 16 pes24nt3 420-pin signal pin-out (part 1 of 3)
18 of 31 april 11, 2007 idt 89hpes24nt3 data sheet f23 v ss k4 v dd ape p1 v dd core u24 v dd pe f24 v dd ape k5 v dd ape p2 v ss u25 pectp05 f25 v dd core k22 v dd ape p3 v tt pe u26 pectn05 f26 v dd core k23 v dd ape p4 v tt pe v1 v dd core g1 pebtn07 k24 v dd ape p5 v ss v2 v ss g2 pebtp07 k25 v ss p22 v ss v3 v dd ape g3 v dd pe k26 v ss p23 v tt pe v4 v dd ape g4 pebrn07 l1 pebtn05 p24 v tt pe v5 v dd ape g5 pebrp07 l2 pebtp05 p25 v ss v22 v dd ape g22 pecrp00 l3 v dd pe p26 v dd core v23 v dd ape g23 pecrn00 l4 pebrn05 r1 pebtn03 v24 v dd ape g24 v dd pe l5 pebrp05 r2 pebtp03 v25 v ss g25 pectp00 l22 pecrp02 r3 v dd pe v26 v dd core g26 pectn00 l23 pecrn02 r4 pebrn03 w1 pebtn01 h1 v ss l24 v dd pe r5 pebrp03 w2 pebtp01 h2 v ss l25 pectp02 r22 pecrp04 w3 v dd pe h3 v tt pe l26 pectn02 r23 pecrn04 w4 pebrn01 h4 v tt pe m1 v dd core r24 v dd pe w5 pebrp01 h5 v ss m2 v ss r25 pectp04 w22 pecrp06 h22 v ss m3 v tt pe r26 pectn04 w23 pecrn06 h23 v tt pe m4 v tt pe t1 v dd core w24 v dd pe h24 v tt pe m5 v ss t2 v ss w25 pectp06 h25 v ss m22 v ss t3 v dd ape w26 pectn06 h26 v ss m23 v tt pe t4 v dd ape y1 v ss j1 pebtn06 m24 v tt pe t5 v ss y2 v ss j2 pebtp06 m25 v ss t22 v ss y3 v tt pe j3 v dd pe m26 v dd core t23 v dd ape y4 v tt pe j4 pebrn06 n1 pebtn04 t24 v dd ape y5 v ss j5 pebrp06 n2 pebtp04 t25 v ss y22 v ss j22 pecrp01 n3 v dd pe t26 v dd core y23 v tt pe j23 pecrn01 n4 pebrn04 u1 pebtn02 y24 v tt pe j24 v dd pe n5 pebrp04 u2 pebtp02 y25 v ss j25 pectp01 n22 pecrp03 u3 v dd pe y26 v ss j26 pectn01 n23 pecrn03 u4 pebrn02 aa1 pebtn00 k1 v ss n24 v dd pe u5 pebrp02 aa2 pebtp00 k2 v ss n25 pectp03 u22 pecrp05 aa3 v dd pe k3 v dd ape n26 pectn03 u23 pecrn05 aa4 pebrn00 pin function alt pin function alt pin function alt pin function alt table 16 pes24nt3 420-pin signal pin-out (part 2 of 3)
19 of 31 april 11, 2007 idt 89hpes24nt3 data sheet aa5 pebrp00 ac3 v dd core ad11 v dd pe ae19 peatp01 aa22 pecrp07 ac4 v dd core ad12 v tt pe ae20 v ss aa23 pecrn07 ac5 v dd core ad13 v dd pe ae21 peatp00 aa24 v dd pe ac6 v tt pe ad14 v tt pe ae22 v ss aa25 pectp07 ac7 pearn07 ad15 v dd pe ae23 v dd core aa26 pectn07 ac8 v dd ape ad16 v dd ape ae24 v dd core ab1 v ss ac9 pearn06 ad17 v ss ae25 v ss ab2 v ss ac10 v dd ape ad18 v dd pe ae26 v ss ab3 v dd core ac11 pearn05 ad19 v dd pe af1 v ss ab4 v dd core ac12 v tt pe ad20 v tt pe af2 v ss ab5 v dd core ac13 pearn04 ad21 v dd pe af3 v dd core ab6 v ss ac14 v tt pe ad22 v ss af4 v dd core ab7 pearp07 ac15 pearn03 ad23 v dd core af5 v dd core ab8 v ss ac16 v dd ape ad24 v dd core af6 v ss ab9 pearp06 ac17 pearn02 ad25 v ss af7 peatn07 ab10 v dd ape ac18 v dd ape ad26 v ss af8 v ss ab11 pearp05 ac19 pearn01 ae1 v ss af9 peatn06 ab12 v ss ac20 v tt pe ae2 v ss af10 v dd core ab13 pearp04 ac21 pearn00 ae3 v dd core af11 peatn05 ab14 v dd ape ac22 v ss ae4 v dd core af12 v dd core ab15 pearp03 ac23 v dd core ae5 v ss af13 peatn04 ab16 v ss ac24 v dd core ae6 v ss af14 v dd core ab17 pearp02 ac25 v ss ae7 peatp07 af15 peatn03 ab18 v dd ape ac26 v ss ae8 v ss af16 v dd core ab19 pearp01 ad1 v ss ae9 peatp06 af17 peatn02 ab20 v ss ad2 v ss ae10 v ss af18 v ss ab21 pearp00 ad3 v dd core ae11 peatp05 af19 peatn01 ab22 v ss ad4 v dd core ae12 v ss af20 v ss ab23 v dd core ad5 v dd core ae13 peatp04 af21 peatn00 ab24 v dd core ad6 v tt pe ae14 v ss af22 v ss ab25 v ss ad7 v ss ae15 peatp03 af23 v dd core ab26 v ss ad8 v dd pe ae16 v ss af24 v dd core ac1 v ss ad9 v ss ae17 peatp02 af25 v ss ac2 v ss ad10 v dd pe ae18 v ss af26 v ss pin function alt pin function alt pin function alt pin function alt table 16 pes24nt3 420-pin signal pin-out (part 3 of 3)
20 of 31 april 11, 2007 idt 89hpes24nt3 data sheet power pins v dd core v dd core v dd core v dd io v dd pe v dd ape v tt pe c4 f2 ae3 b3 g3 f3 h3 c14 f25 ae4 b24 g24 f24 h4 c16 f26 ae23 c5 j3 k3 h23 d5 m1 ae24 c7 j24 k4 h24 d6 m26 af3 c9 l3 k5 m3 d8 p1 af4 c11 l24 k22 m4 d10 p26 af5 c13 n3 k23 m23 d12 t1 af10 c15 n24 k24 m24 d13 t26 af12 c17 r3 t3 p3 d15 v1 af14 c19 r24 t4 p4 d17 v26 af16 c21 u3 t23 p23 d18 ab3 af23 c23 u24 t24 p24 d19 ab4 af24 w3 v3 y3 d21 ab5 w24 v4 y4 d22 ab23 aa3 v5 y23 e6 ab24 aa24 v22 y24 e7 ac3 ad8 v23 ac6 e9 ac4 ad10 v24 ac12 e11 ac5 ad11 ab10 ac14 e13 ac23 ad13 ab14 ac20 e15 ac24 ad15 ab18 ad6 e17 ad3 ad18 ac8 ad12 e19 ad4 ad19 ac10 ad14 e20 ad5 ad21 ac16 ad20 e21 ad23 ac18 f1 ad24 ad16 table 17 pes24nt3 power pins
21 of 31 april 11, 2007 idt 89hpes24nt3 data sheet ground pins v ss v ss v ss v ss v ss a1 d11 h1 y22 ae2 a2 d14 h2 y25 ae5 a3 d16 h5 y26 ae6 a23 d20 h22 ab1 ae8 a24 d23 h25 ab2 ae10 a25 d24 h26 ab6 ae12 a26 d25 k1 ab8 ae14 b1 e1 k2 ab12 ae16 b2 e2 k25 ab16 ae18 b25 e3 k26 ab20 ae20 b26 e4 m2 ab22 ae22 c2 e5 m5 ab25 ae25 c3 e8 m22 ab26 ae26 c6 e10 m25 ac1 af1 c8 e12 p2 ac2 af2 c10 e14 p5 ac22 af6 c12 e16 p22 ac25 af8 c18 e18 p25 ac26 af18 c20 e22 t2 ad1 af20 c22 e23 t5 ad2 af22 c24 e24 t22 ad7 af25 c25 e25 t25 ad9 af26 d2 e26 v2 ad17 d3 f4 v25 ad22 d4 f5 y1 ad25 d7 f22 y2 ad26 d9 f23 y5 ae1 table 18 pes24nt3 ground pins
22 of 31 april 11, 2007 idt 89hpes24nt3 data sheet alternate signal functions signals listed alphabetically pin gpio alternate b18 gpio[0] pebrstn a19 gpio[1] pecrstn b19 gpio[2] palinkupn a20 gpio[3] pblinkupn b20 gpio[4] pclinkupn a21 gpio[5] failoverp table 19 pes24nt3 alternate signal functions signal name i/o type location signal category cclkds i a13 system cclkus i a12 gpio_00 i/o b18 general purpose input/output gpio_01 i/o a19 gpio_02 i/o b19 gpio_03 i/o a20 gpio_04 i/o b20 gpio_05 i/o a21 gpio_06 i/o b21 gpio_07 i/o a22 jtag_tck i b4 jtag jtag_tdi i a4 jtag_tms i a5 jtag-tdo o b5 jtag-trst_n i b6 msmbaddr_1 i a6 smbus msmbaddr_2 i b7 msmbaddr_3 i a7 msmbaddr_4 i b8 msmbclk i/o a8 msmbdat i/o b9 msmbsmode i b22 system table 20 89pes24nt3 alphabetical signal list (part 1 of 5)
23 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pealrev i b13 pci express pearn00 i ac21 pearn01 i ac19 pearn02 i ac17 pearn03 i ac15 pearn04 i ac13 pearn05 i ac11 pearn06 i ac9 pearn07 i ac7 pearp00 i ab21 pearp01 i ab19 pearp02 i ab17 pearp03 i ab15 pearp04 i ab13 pearp05 i ab11 pearp06 i ab9 pearp07 i ab7 peatn00 o af21 peatn01 o af19 peatn02 o af17 peatn03 o af15 peatn04 o af13 peatn05 o af11 peatn06 o af9 peatn07 o af7 peatp00 o ae21 peatp01 o ae19 peatp02 o ae17 peatp03 o ae15 peatp04 o ae13 peatp05 o ae11 peatp06 o ae9 peatp07 o ae7 peblrev i a14 pebrn00 i aa4 pebrn01 i w4 signal name i/o type location signal category table 20 89pes24nt3 alphabetical signal list (part 2 of 5)
24 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pebrn02 i u4 pci express pebrn03 i r4 pebrn04 i n4 pebrn05 i l4 pebrn06 i j4 pebrn07 i g4 pebrp00 i aa5 pebrp01 i w5 pebrp02 i u5 pebrp03 i r5 pebrp04 i n5 pebrp05 i l5 pebrp06 i j5 pebrp07 i g5 pebtn00 o aa1 pebtn01 o w1 pebtn02 o u1 pebtn03 o r1 pebtn04 o n1 pebtn05 o l1 pebtn06 o j1 pebtn07 o g1 pebtp00 o aa2 pebtp01 o w2 pebtp02 o u2 pebtp03 o r2 pebtp04 o n2 pebtp05 o l2 pebtp06 o j2 pebtp07 o g2 peclrev i b16 pecrn00 i g23 pecrn01 i j23 pecrn02 i l23 pecrn03 i n23 pecrn04 i r23 signal name i/o type location signal category table 20 89pes24nt3 alphabetical signal list (part 3 of 5)
25 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pecrn05 i u23 pci express pecrn06 i w23 pecrn07 i aa23 pecrp00 i g22 pecrp01 i j22 pecrp02 i l22 pecrp03 i n22 pecrp04 i r22 pecrp05 i u22 pecrp06 i w22 pecrp07 i aa22 pectn00 o g26 pectn01 o j26 pectn02 o l26 pectn03 o n26 pectn04 o r26 pectn05 o u26 pectn06 o w26 pectn07 o aa26 pectp00 o g25 pectp01 o j25 pectp02 o l25 pectp03 o n25 pectp04 o r25 pectp05 o u25 pectp06 o w25 pectp07 o aa25 pentbrstn i b17 system perefclkn1 i c1 pci express perefclkn2 i d26 perefclkp1 i d1 perefclkp2 i c26 perstn i a17 system refclkm i b23 pci express rsthalt i a18 system signal name i/o type location signal category table 20 89pes24nt3 alphabetical signal list (part 4 of 5)
26 of 31 april 11, 2007 idt 89hpes24nt3 data sheet ssmbaddr_1 i a9 smbus ssmbaddr_2 i b10 ssmbaddr_3 i a10 ssmbaddr_5 i b11 ssmbclk i/o a11 smbus ssmbdat i/o b12 swmode_0 i b14 system swmode_1 i a15 swmode_2 i b15 swmode_3 i a16 system v dd core, v dd ape, v dd io, v dd pe , v tt pe see table 17 for a listing of power pins. v ss see table 18 for a listing of ground pins. signal name i/o type location signal category table 20 89pes24nt3 alphabetical signal list (part 5 of 5)
27 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pes24nt3 pinout ? top view 1 2 3 4 5 6 7 8 9 10 1112 13141516 vss (ground) v dd core (power) a b v dd i/o (power) 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af v tt pe (power) v dd pe (power) v dd ape (power) signals x x x x x x x x x x x x x x x x x x x x x x x x x
28 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pes24nt3 package drawing ? 420-pin bx420/bxg420
29 of 31 april 11, 2007 idt 89hpes24nt3 data sheet pes24nt3 package drawing ? page two
30 of 31 april 11, 2007 idt 89hpes24nt3 data sheet revision history march 15, 2007 : initial publication of preliminary data sheet. april 11, 2007 : in table 2, revised description of msmbclk.
31 of 31 april 11, 2007 idt 89hpes24nt3 data sheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 ? ordering information valid combinations 89hpes24nt3zabx 420-pin bx420 package, commercial temperature 89HPES24NT3ZABXG 420-pin green bx420 package, commercial temperature nn aaaa nnan aa a operating voltage device family product package temp range h blank commercial temperature (0c to +70c ambient) product family 89 serial switching product bx420 420-ball bga bx 24nt3 24-lane, 3-port 1.0v +/- 0.1v core voltage detail pci express switch pes legend a = alpha character n = numeric character bxg420 420-ball bga, green bxg aa revision id za silicon revision non-transparent

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